1. Technical Field
Various embodiments generally relate to a semiconductor device and a driving method thereof, and more particularly, to a semiconductor device including an error correction code circuit.
2. Related Art
A typical semiconductor device includes a plurality of memory cell arrays having a plurality of unit cells for storing and outputting data according to addresses, and a plurality of sense amplifier arrays for amplifying and outputting data signals outputted from the cell arrays.
Recently, as relates to a semiconductor memory device, there have been increasing efforts to develop a technology for increasing net dies in order to improve manufacturing costs. Among the efforts, there has been proposed a way of converting a cell array structure of 8F2 into a cell array structure of 6F2 or 4F2. The cell array structure of 6F2 has recently and continuously been spotlighted because integration of many more cells per unit area is possible as compared with the cell array structure of 8F2.
In general, the 8F2 employs a folded bit line structure and the 6F2 employs an open bit line structure. In the folded bit line structure, a bit line BL and a bit bar line BLB are formed on one side of a sense amplifier, and in the open bit line structure, the bit line BL and the bit bar line BLB are formed at both sides of the sense amplifier.
The open bit line structure will be described in detail below. A semiconductor device having the open bit line structure includes a plurality of memory cell mats, a plurality of sense amplifier arrays S/A arrays, and a dummy mat.
In each of the plurality of memory cell mats, memory cells for storing data may be formed. The memory cells are arranged in crossing areas of bit lines and word lines and crossing areas of bit bar lines BLB and sub-word lines SWL. The memory cell includes an NMOS transistor which is a cell transistor and a cell capacitor.
The dummy mat is a mat arranged at the uppermost end and the lowermost end of the memory cell mat, that is, at the outer peripheral portion of a memory cell block. Further, the dummy mat is arranged at a lower end of a target cell mat to provide the target cell mat with a level of a bit bar line to be compared with. With such a dummy mat, a plurality of bit lines and a plurality of dummy word lines which are arranged to cross each other may be formed in a manner similar to each memory cell array block.
However, in the dummy mat, since only a bit bar line (or a bit line), which is compared with the target cell mat and is connected to a sense amplifier, actually operates, a bit line (or a bit bar line) in the dummy mat does not operate and unnecessarily occupies an area. Therefore, net dies may be reduced.
Furthermore, as a voltage that is applied to a memory cell is lowered and a cell size is reduced, deterioration of a soft error tolerance has been problematic. In a semiconductor integrated device using an ECC (Error Correction code) circuit for correcting data errors, a circuit technology for adding a parity bit to typical data and correcting a failed bit has been proposed.